The present invention relates to a dynamic RAM (Random Access Memory), particularly to a technique effectively used as a defect relief technique for a synchronous DRAM.
A redundant circuit of a dynamic RAM is disclosed in Japanese Patent Laid-Open Nos. 64-76597/1989, 4-286798/1992, 7-282597/1995, 7-105697/1995, and 9-128993/1997.
A dynamic RAM provided with a defect relief circuit for switching a defective word line to a redundant word line determines whether an input address signal indicates a defective address. When an access is to a defective word line, the selecting operation on the normal circuit side is inhibited so as to select a redundant word line. Therefore, the time taken to select a normal word line having no defect is wasted. The same holds true for the case where a word line having no detect is selected, because a decision that the address signal is not indicative of a defective address is necessary in accordance with the comparison result of the defective address as a condition of the selecting operation of the normal word line.